The most well-known coin to implement X16R is Ravencoin (RVN), for which this algorithm was initially created, though the algorithm is a descendent of X11, initially created for use with Dash (DASH).
Compared to Ethereum and Monero, the prominence of Ravencoin in the mainstream mining world is relatively new. The algorithm X16R is notable for bringing a different approach than the previously-mentioned algorithms, to ASIC resistance.
Similar to the X11 algorithm from which it is descended, which ran 11 hash functions in series, X16R runs 16 hash functions in series.
X11 was, in due course, implemented in an ASIC, removing its relevance to CPU or GPU mining. X16R seeks to be problematic to implement in an ASIC by causing which of the 16 hash functions are used, and in what order they are used, to vary with each new block on Ravencoin’s blockchain.
The way this works is that the end of the previous block’s hash value determines the current block’s sequence of hash functions. The final 64 bits is split into sixteen 4-bit values, that describe, in order, which of the 16 hash functions defined in X16R are to be used.
As well as this making X16R much more challenging to implement in an ASIC, it also means that, depending on which of the hash functions are included in a particular block, a given GPU’s hash rate, for that block, will be different than it was for other blocks. The hash rate is governed by the overall complexity of the mix of included hash functions for that block.
The variance of hash rate per block has proven vexatious to some in the mining community, as it impedes conventional benchmarking methods, as well as short-term calculations of mining value. However, because blocks’ hash values are fairly random, then over a long period of time, average hash rates still remain a meaningful indicator, as all X16R’s hash functions are equally as likely to occur.
Unlike with Ethereum and Monero, the method of ASIC resistance used by Ravencoin is not as intense on a GPU’s memory, and so miners will instead usually prefer to implement core clock frequency increases instead. In fact, it’s common to reduce the memory clock frequency to reduce power and heat in this case.
